- Patent Title: Programming memories with stepped programming pulses including inhibiting a memory cell for a portion of a programming pulse and enabling that memory cell for another portion of that programming pulse
-
Application No.: US15687710Application Date: 2017-08-28
-
Publication No.: US10037797B2Publication Date: 2018-07-31
- Inventor: Qiang Tang , Xiaojiang Guo , Ramin Ghodsi
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G11C11/56 ; G11C16/12 ; G11C16/04 ; G11C16/34 ; G06F3/06 ; G06F12/02 ; G11C16/10
Abstract:
Methods of operating a memory device include applying a programming pulse to a plurality of memory cells selected for programming having an initial portion having a first voltage level and a subsequent portion having a second voltage level less than the first voltage level, inhibiting a particular memory cell of the plurality of memory cells from programming during the initial portion of the programming pulse while a different memory cell of the plurality of memory cells is enabled for programming, and inhibiting the different memory cell from programming during the subsequent portion of the programming pulse while the particular memory cell is enabled for programming.
Public/Granted literature
- US20170352409A1 PROGRAMMING MEMORIES WITH STEPPED PROGRAMMING PULSES Public/Granted day:2017-12-07
Information query
