Invention Grant
- Patent Title: Inter-fan-out wafer level packaging with coaxial TIV for 3D IC low-noise packaging
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Application No.: US15431909Application Date: 2017-02-14
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Publication No.: US10037897B2Publication Date: 2018-07-31
- Inventor: Feng-Wei Kuo , Wen-Shiang Liao
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/48 ; H01L23/498 ; H01L25/065 ; H01L23/522 ; H01L23/532 ; H01L23/552 ; H01L25/00

Abstract:
A semiconductor package includes a first semiconductor element, an insulating layer, and a second semiconductor element. The first semiconductor element includes at least one conductive layer and at least one via layer. The insulating layer is positioned above the first semiconductor device and includes at least one through insulator via (TIV) extending from a first side of the insulating layer to a second side of the insulating layer. The at least one TIV has a conductive core including a copper-containing material. The second semiconductor element is positioned above the insulating layer and includes at least one conductive layer and at least one via layer. The at least one TIV couples the at least one via layer of the first semiconductor element to the at least one via layer of the second semiconductor element.
Public/Granted literature
- US20180151389A1 INTER-FAN-OUT WAFER LEVEL PACKAGING WITH COAXIAL TIV FOR 3D IC LOW-NOISE PACKAGING Public/Granted day:2018-05-31
Information query
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