Invention Grant
- Patent Title: Thermally enhanced semiconductor package having field effect transistors with back-gate feature
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Application No.: US15652867Application Date: 2017-07-18
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Publication No.: US10037929B2Publication Date: 2018-07-31
- Inventor: Julio C. Costa , George Maxim , Dirk Robert Walter Leipold , Baker Scott
- Applicant: Qorvo US, Inc.
- Applicant Address: US NC Greensboro
- Assignee: Qorvo US, Inc.
- Current Assignee: Qorvo US, Inc.
- Current Assignee Address: US NC Greensboro
- Agency: Withrow & Terranova, P.L.L.C.
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L29/423 ; H01L23/373 ; H01L29/786 ; H01L29/06 ; H01L23/535 ; H01L23/00 ; H01L23/498 ; H01L23/31

Abstract:
The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a non-silicon thermal conductive component, a silicon layer with a thickness between 100 Å and 10 μm over the thermal conductive component, a buried oxide (BOX) layer over the silicon layer, an epitaxial layer over the BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the silicon layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
Public/Granted literature
- US10079196B2 Thermally enhanced semiconductor package having field effect transistors with back-gate feature Public/Granted day:2018-09-18
Information query
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