Invention Grant
- Patent Title: Reliable packaging and interconnect structures
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Application No.: US15623228Application Date: 2017-06-14
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Publication No.: US10037940B2Publication Date: 2018-07-31
- Inventor: Cyprian Emeka Uzoh , Belgacem Haba , Craig Mitchell
- Applicant: Tessera, Inc.
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/532 ; H01L21/768 ; H01L23/522 ; H01L23/48 ; H01L21/321 ; H01L21/288

Abstract:
Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.
Public/Granted literature
- US20170294376A1 Reliable packaging and interconnect structures Public/Granted day:2017-10-12
Information query
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