Invention Grant
- Patent Title: ESD protection structure and method of fabrication thereof
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Application No.: US14830038Application Date: 2015-08-19
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Publication No.: US10037986B2Publication Date: 2018-07-31
- Inventor: Jean Philippe Laine , Patrice Besse
- Applicant: Freescale Semiconductor, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Priority: WOPCT/IB2015/000536 20150319
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L29/02 ; H01L29/66 ; H01L21/02 ; H01L27/02 ; H01L29/74 ; H01L21/762 ; H01L21/761 ; H01L29/735

Abstract:
An ESD protection structure formed within an isolation trench and comprising a first peripheral semiconductor region of a first doping type, a second semiconductor region of the first doping type, and a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the semiconductor regions of the first doping type and isolation between the further semiconductor region of the first doping type and the isolation trench. The semiconductor structure of the second doping type is formed such that no semiconductor region of the second doping type is formed between a peripheral side of the first semiconductor region of the first doping type and a wall of the isolation trench, and no semiconductor region of the first doping type is in contact with the isolation trench other than the first semiconductor region of the first doping type.
Public/Granted literature
- US20160276332A1 ESD PROTECTION STRUCTURE AND METHOD OF FABRICATION THEREOF Public/Granted day:2016-09-22
Information query
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