Invention Grant
- Patent Title: Method of manufacturing interconnect layer and semiconductor device which includes interconnect layer
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Application No.: US15255394Application Date: 2016-09-02
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Publication No.: US10037990B2Publication Date: 2018-07-31
- Inventor: Chin-Shan Wang , Shun-Yi Lee
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L23/528 ; H01L21/822 ; H01L21/8234 ; H01L23/535 ; H01L49/02 ; H01L29/06 ; H01L21/768

Abstract:
A semiconductor device includes an interconnect layer on an inter-layer dielectric (ILD) structure. The ILD structure includes: first contacts, extending through the ILD structure, electrically connected to corresponding first components located in a floor structure underlying the ILD structure; at least one second component located within the ILD structure and spaced from a surface of the ILD structure (in a direction perpendicular to a plane of the ILD structure) a distance which is less than a thickness of the ILD structure; and second contacts directly contacting corresponding first regions of the at least one second component. The interconnect layer includes: first metallization segments which directly contact corresponding ones of the first contacts; and second metallization segments located over a second region of the at least one second component, a width of the second metallization segments being less than a width of the first metallization segments.
Public/Granted literature
- US20180006017A1 METHOD OF MANUFACTURING INTERCONNECT LAYER AND SEMICONDUCTOR DEVICE WHICH INCLUDES INTERCONNECT LAYER Public/Granted day:2018-01-04
Information query
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