An all digital phase locked loop (ADPLL) includes an integer part phase processing circuit that outputs an integer part frequency signal using a first value and a second value. The first value is obtained by counting edges of one of a plurality of output clock signals. The second value indicates current edge position information on an edge position of an external reference clock signal with respect to the plurality of output clock signals. The ADPLL further includes a fraction part phase processing circuit that selects two adjacent output clock signals of the plurality of output clock signals according to a prediction selection signal and that generates a fraction part frequency signal using the fraction part phase signal, the prediction selection signal being generated according to a fraction part phase signal indicating fraction part phase information and a signal indicating the current edge position information.