Invention Grant
- Patent Title: Interface chip and test method therefor
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Application No.: US15411063Application Date: 2017-01-20
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Publication No.: US10041999B2Publication Date: 2018-08-07
- Inventor: Shih-Hao Chen
- Applicant: VIA TECHNOLOGIES, INC.
- Applicant Address: TW New Taipei
- Assignee: VIA TECHNOLOGIES, INC.
- Current Assignee: VIA TECHNOLOGIES, INC.
- Current Assignee Address: TW New Taipei
- Agency: McClure, Qualey & Rodack, LLP
- Priority: TW105141176A 20161213
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G01R31/3177

Abstract:
A built-in self-test mechanism for an interface chip. During a loopback test procedure, a transmission terminal of the interface chip is coupled back to the interface chip by a reception terminal of the interface chip and a loopback test circuit within the interface chip generates a test sequence which includes a synchronization section and a section of repeated test code. The test sequence is scrambled by a scrambler and then is transmitted via the transmission terminal and looped back to the reception terminal. The signal looped back to the reception terminal is processed by an equalizer and descrambled by a descrambler to be further checked by the loopback test circuit for determining whether the interface chip is functioning normally. The dynamically-changed keys used in the scrambler and the descrambler are synchronized according to the synchronization section. The equalizer is optimized by the scrambled section of repeated test code.
Public/Granted literature
- US20180164374A1 INTERFACE CHIP AND TEST METHOD THEREFOR Public/Granted day:2018-06-14
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