An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.