Invention Grant
- Patent Title: Method of manufacturing semiconductor device having semiconductor chip mounted on lead frame
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Application No.: US15495058Application Date: 2017-04-24
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Publication No.: US10043721B2Publication Date: 2018-08-07
- Inventor: Yasuhiro Taguchi
- Applicant: SII Semiconductor Corporation
- Applicant Address: JP
- Assignee: SEIKO INSTRUMENTS INC.
- Current Assignee: SEIKO INSTRUMENTS INC.
- Current Assignee Address: JP
- Agency: Adams & Wilks
- Priority: JP2014-056450 20140319
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/48 ; H01L21/50 ; H01L21/66 ; H01L23/00 ; H01L23/498 ; H01L23/495 ; H01L21/56
Abstract:
In the manufacture of a semiconductor device using a lead frame, in which an outer lead is electrically connected to an inner lead suspension lead via an inner lead, an encapsulating resin is formed over the inner lead, part of the outer lead, and part of the inner lead suspension lead. The parts of the outer lead and the inner lead suspension lead that protrude from the resin are cut, and a plated film is formed on the portion of the cut outer lead that protrudes from the resin so that a solder layer is easily formed on all exposed surfaces of the outer lead. The inner lead suspension lead includes a narrowed portion that is smaller in cross-sectional area than other portions of the inner lead suspension lead, and an outline of the resin overlaps the narrowed portion of the inner lead suspension lead in plan view so as to suppress impact forces generated when the inner lead suspension lead is cut at the narrowed portion.
Public/Granted literature
- US20170229355A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR CHIP MOUNTED ON LEAD FRAME Public/Granted day:2017-08-10
Information query
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