Invention Grant
- Patent Title: Stacked silicon package assembly having an enhanced lid
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Application No.: US14867349Application Date: 2015-09-28
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Publication No.: US10043730B2Publication Date: 2018-08-07
- Inventor: Gamal Refai-Ahmed , Tien-Yu Lee , Ferdinand F. Fernandez , Suresh Ramalingam , Ivor G. Barber , Inderjit Singh , Nael Zohni
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent Keith Taboada
- Main IPC: H01L23/10
- IPC: H01L23/10 ; H01L23/367 ; H01L25/065 ; H01L23/373 ; H01L25/00 ; H01L23/16 ; H01L25/18 ; H01L23/04 ; H01L23/473 ; H01L21/48 ; H01L23/00 ; H01L23/40

Abstract:
A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.
Public/Granted literature
- US20170092619A1 STACKED SILICON PACKAGE ASSEMBLY HAVING AN ENHANCED LID Public/Granted day:2017-03-30
Information query
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