Invention Grant
- Patent Title: Fully depleted silicon on insulator integration
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Application No.: US15660288Application Date: 2017-07-26
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Publication No.: US10043826B1Publication Date: 2018-08-07
- Inventor: Xia Li , Bin Yang , Gengming Tao
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Patterson & Sheridan, LLP
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L27/12 ; H01L29/08 ; H01L29/36 ; H01L29/10 ; H01L29/06 ; H01L29/78 ; H01L29/45 ; H01L21/762 ; H01L29/66 ; H01L21/265 ; H01L21/84 ; H01L21/683 ; H01L21/02 ; H01L21/8234

Abstract:
Certain aspects of the present disclosure generally relate to a semiconductor device. The semiconductor device generally includes a substrate, a first non-insulative region disposed above the substrate, and a second non-insulative region disposed above the first non-insulative region, wherein the first and second non-insulative regions have the same doping type and different doping concentrations. In certain aspects, the semiconductor device also includes a first dielectric layer, a channel region, the first dielectric layer being disposed adjacent to a first side of the channel region, a second dielectric layer disposed adjacent to a second side of the channel region, and a third non-insulative region disposed above the second dielectric layer. In certain aspects, the semiconductor device also includes a fourth non-insulative region disposed adjacent to a third side of the channel region, and a fifth non-insulative region disposed adjacent to a fourth side of the channel region.
Information query
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