Invention Grant
- Patent Title: Compensating for parasitic voltage drops in circuit arrays
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Application No.: US15841670Application Date: 2017-12-14
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Publication No.: US10043855B1Publication Date: 2018-08-07
- Inventor: Sapan Agarwal , Matthew Marinella
- Applicant: National Technology & Engineering Solutions of Sandia, LLC
- Applicant Address: US NM Albuquerque
- Assignee: National Technology & Engineering Solutions of Sandia, LLC
- Current Assignee: National Technology & Engineering Solutions of Sandia, LLC
- Current Assignee Address: US NM Albuquerque
- Agency: Medley, Behrens & Lewis, LLC
- Main IPC: H01L27/24
- IPC: H01L27/24 ; G11C13/00 ; H01L27/15 ; G11C5/14 ; H01L45/00 ; H01L27/32 ; G11C5/06 ; H01L49/02

Abstract:
Various technologies for improving uniformity of operation of elements in an array circuit are described herein. In an exemplary embodiment, a plurality of resistive elements are incorporated into an array circuit such that voltages developed across any two elements is substantially the same when an equal voltage is applied to energize the elements. In a crossbar array circuit that comprises a plurality of elements arranged in rows and columns, the resistance of each of the resistive elements is based upon a row or column to which the resistive element is connected.
Information query
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