Invention Grant
- Patent Title: Semiconductor device and method of manufacturing the same
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Application No.: US14795839Application Date: 2015-07-09
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Publication No.: US10043881B2Publication Date: 2018-08-07
- Inventor: Yoshiki Yamamoto
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2014-141814 20140709
- Main IPC: H01L29/49
- IPC: H01L29/49 ; H01L21/84 ; H01L29/51 ; H01L27/12 ; H01L29/06

Abstract:
While increasing a threshold voltage of a MOSFET configuring a CMOS, electric power saving of elements is achieved by suppressing excessive increase in the threshold voltage, and occurrence of performance variation among the elements is suppressed. A gate electrode of an NMOS is made of a P-type semiconductor film, a high-permittivity film is provided in a gate insulating film of the NMOS, and an impurity is prevented from being introduced into a channel region of the NMOS. Moreover, a high-permittivity film is provided also in a gate insulating film of a PMOS.
Public/Granted literature
- US20160013287A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2016-01-14
Information query
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