A clock data recovery (CDR) circuit includes: a band select circuit, a low dropout regulator (LDO), a charge pump and a voltage-controlled oscillator (VCO), wherein the band select circuit is arranged to generate a digital signal according to at least a reference voltage; the LDO is arranged to regulate a ground voltage, wherein the LDO adjusts an operating band of the LDO by receiving at least a part of the digital signal to adjust a bias current of an amplifier of the LDO; the charge pump is arranged to generate a control voltage according to at least a part of the digital signal; and the VCO is arranged to generate a clock signal according to the control voltage, wherein the VCO adjusts an operating band of the CDR circuit by receiving at least a part of the digital signal to adjust a bias current of the VCO.