Invention Grant
- Patent Title: Apparatuses and methods for a memory device with dual common data I/O lines
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Application No.: US15719349Application Date: 2017-09-28
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Publication No.: US10049722B2Publication Date: 2018-08-14
- Inventor: Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Atsuo Koshizuka
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C5/06
- IPC: G11C5/06 ; G11C11/4093 ; G11C11/408 ; G11C11/4076 ; G11C11/4074 ; G11C11/4097 ; G11C11/4096 ; G11C11/4091

Abstract:
Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.
Public/Granted literature
- US20180197595A1 APPARATUSES AND METHODS FOR A MEMORY DEVICE WITH DUAL COMMON DATA I/O LINES Public/Granted day:2018-07-12
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