- Patent Title: Two-level and multi-level data storage semiconductor memory device
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Application No.: US14918036Application Date: 2015-10-20
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Publication No.: US10049749B2Publication Date: 2018-08-14
- Inventor: Noboru Shibata
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz & Volek PC
- Priority: JP2013-029342 20130218
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C16/26 ; G11C11/56 ; G11C16/04

Abstract:
A semiconductor includes a memory cell, a bit line, a word line, a sense amplifier, and a control circuit. The memory cell stores n levels (where n is a natural number of two or greater). The control circuit controls potentials of the word line and the bit line. In a read of k−1 levels (k≤n) stored in the memory cell, the control circuit, upon applying a given voltage to the word line, determines read data based on first data corresponding to the voltage of the bit line read at a first timing by the sense amplifier and second data corresponding to the voltage of the bit line read, by the sense amplifier, at a second timing different from the first timing.
Public/Granted literature
- US20160042800A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2016-02-11
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