- Patent Title: Semiconductor device including a target integrated circuit pattern
-
Application No.: US15436147Application Date: 2017-02-17
-
Publication No.: US10049919B2Publication Date: 2018-08-14
- Inventor: Chieh-Han Wu , Cheng-Hsiung Tsai , Chung-Ju Lee , Ming-Feng Shieh , Ru-Gun Liu , Shau-Lin Shue , Tien-I Bao
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/311 ; H01L21/033

Abstract:
A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.
Public/Granted literature
- US20170162435A1 METHOD OF SPACER PATTERNING TO FORM A TARGET INTEGRATED CIRCUIT PATTERN Public/Granted day:2017-06-08
Information query
IPC分类: