A circuit for pulse duty factor limitation in a switch mode regulator, having an output stage to which control is applied by a signal, is described, in which circuit a pulse duty factor limiter is connected to the switch mode regulator in order to transfer the signal to the pulse duty factor limiter; the pulse duty factor limiter is configured to generate from the signal a limited signal limited at the top end in terms of pulse duty factor; and the pulse duty factor limiter is connected to the output stage in order to transfer the limited signal to the output stage. Also proposed is a method for operating a switch mode regulator having a downstream circuit to which control is applied by a signal of the switch mode regulator and having a capacitor that becomes charged when the downstream circuit is switched off, in which method the pulse duty factor of the signal is limited at an upper limit value in such a way that a predetermined charging time for the capacitor is available.