System on chip power management
Abstract:
An implementation of a system disclosed herein provides an apparatus, comprising a system on chip, wherein the system on chip is configured to receive a sleep command from a host and in response to the sleep command, calculate a primary checksum of a block of data from a low latency memory such as a tightly coupled memory (TCM), copy the primary checksum and the block of data into a volatile storage media, preserve interface variables of the system on chip in the volatile storage media, operate the volatile storage media in a self-refresh mode, and shut down power to other components on the system on chip.
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