A gate drive integrated circuit (IC) for a display device includes a start pulse modulator configured to receive a start pulse or a front-end carry pulse alternating between a first logic level and a second logic level to output a modulation start pulse or a modulation carry pulse that is generated by modulating a logic level shift time of the start pulse or the front-end carry pulse; and a shift register configured to receive and sequentially output the modulation start pulse or the modulation carry pulse. The start pulse modulator is further configured to output the modulation start pulse or the modulation carry pulse having the second logic level at a time when a logic level of the start pulse or the front-end carry pulse has a third logic level between the first logic level and the second logic level.