A memory system is disclosed. The memory system includes: a memory; a first ECC circuit used to encode information bits of a first length into a codeword of a first ECC scheme, and to decode a codeword of the first ECC scheme read from the memory into decoded information bits of the first length; a second ECC circuit used to encode information bits of a second length into a codeword of a second ECC scheme, and to decode a codeword of the second ECC scheme read from the memory into decoded information bits of the second length; and a control circuit used to combine a plurality sets of the decoded information bits of the first length into the information bits of the second length, and to separate the decoded information bits of the second length into a plurality sets of the information bits of the first length.