A signal recovery circuit includes an oscillator configured to control a frequency of generating first clock, and a feedback circuit configured to control the oscillator in order that input data is synchronized with the first clock in accordance with a phase relation between the input data and the first clock, wherein the feedback circuit includes a controller configured to control the oscillator in accordance with the phase relation between the input data and the first clock, a first phase detector configured to generate a clock phase control signal in accordance with the phase relation between the input data and the first clock, and a state detection circuit configured to detect whether the signal recovery circuit is in a locked state or an unlocked state, based on a magnitude of an amplitude of a first component or a second component of the clock phase control signal.