Invention Grant
- Patent Title: Pattern weakness and strength detection and tracking during a semiconductor device fabrication process
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Application No.: US15709856Application Date: 2017-09-20
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Publication No.: US10062160B2Publication Date: 2018-08-28
- Inventor: Khurram Zafar , Chenmin Hu , Ye Chen , Yue Ma , Chingyun Hsiang , Justin Chen , Raymond Xu , Abhishek Vikram , Ping Zhang
- Applicant: Anchor Semiconductor Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Anchor Semiconductor Inc.
- Current Assignee: Anchor Semiconductor Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Van Pelt, Yi & James LLP
- Main IPC: G06K9/00
- IPC: G06K9/00 ; G06T7/00 ; G06K9/46 ; G06K9/62 ; G06K9/52

Abstract:
Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.
Public/Granted literature
- US20180033132A1 PATTERN WEAKNESS AND STRENGTH DETECTION AND TRACKING DURING A SEMICONDUCTOR DEVICE FABRICATION PROCESS Public/Granted day:2018-02-01
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