Invention Grant
- Patent Title: Memory architecture with ECC and method for operating memory with ECC
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Application No.: US15394821Application Date: 2016-12-30
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Publication No.: US10062446B2Publication Date: 2018-08-28
- Inventor: Po-Hao Huang
- Applicant: eMemory Technology Inc.
- Applicant Address: TW Hsinchu
- Assignee: eMemory Technology Inc.
- Current Assignee: eMemory Technology Inc.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: G11C17/18
- IPC: G11C17/18 ; G11C17/16 ; G06F12/14 ; H04L9/32 ; G11C29/00 ; G11C16/22 ; G11C7/24 ; G06F21/73 ; G11C16/04 ; G11C16/08 ; G11C16/24 ; G11C16/26 ; G11C16/32 ; G06F3/06 ; G06F11/10 ; G06F21/72 ; H03K3/356 ; G11C7/10 ; G11C7/22 ; G11C5/06 ; H01L27/112
Abstract:
A circuit architecture for operating error-correction code (ECC) in a memory apparatus includes a control circuit and an ECC circuit. The ECC circuit is coupled with the control circuit. The control circuit receives a first data of a set of bits to invert the first data as an inverted data. The ECC circuit receives the inverted data for encryption or decryption and outputs an ECC-processed data. The control circuit inverts the ECC-processed data as a second data.
Public/Granted literature
- US20170206134A1 MEMORY ARCHITECTURE WITH ECC AND METHOD FOR OPERATING MEMORY WITH ECC Public/Granted day:2017-07-20
Information query
