Invention Grant
- Patent Title: SOI integrated circuit equipped with a device for protecting against electrostatic discharges
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Application No.: US15591565Application Date: 2017-05-10
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Publication No.: US10062681B2Publication Date: 2018-08-28
- Inventor: Yohann Solaro , Sorin Cristoloveanu , Claire Fenouillet-Beranger , Pascal Fonteneau
- Applicant: Commissariat à l'énergie atomique et aux énergies alternatives , STMicroelectronics SA , Centre National de la Recherche Scientifique
- Applicant Address: FR Paris FR Montrouge FR Paris
- Assignee: Commissariat à l'énergie atomique et aux énergies alternatives,STMicroelectronics SA,Centre National de la Recherche Scientifique
- Current Assignee: Commissariat à l'énergie atomique et aux énergies alternatives,STMicroelectronics SA,Centre National de la Recherche Scientifique
- Current Assignee Address: FR Paris FR Montrouge FR Paris
- Agency: Occhiuti & Rohlicek LLP
- Priority: FR1357769 20130805
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L29/78 ; H01L29/74 ; H01L29/749 ; H01L29/747 ; H01L29/66 ; H01L29/423 ; H01L29/10 ; H01L27/12
Abstract:
A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.
Public/Granted literature
- US20170256531A1 SOI INTEGRATED CIRCUIT EQUIPPED WITH A DEVICE FOR PROTECTING AGAINST ELECTROSTATIC DISCHARGES Public/Granted day:2017-09-07
Information query
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