Invention Grant
- Patent Title: Leakage tolerant oscillator
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Application No.: US15140717Application Date: 2016-04-28
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Publication No.: US10063188B2Publication Date: 2018-08-28
- Inventor: Shail Srinivas
- Applicant: Silicon Laboratories Inc.
- Applicant Address: US TX Austin
- Assignee: Silicon Laboratories Inc.
- Current Assignee: Silicon Laboratories Inc.
- Current Assignee Address: US TX Austin
- Agency: Zagorin Cave LLP
- Main IPC: H03K17/00
- IPC: H03K17/00 ; H03B5/36 ; H03B5/24 ; H01L21/00 ; H03K17/06 ; H03B5/34 ; H03L5/02 ; H03K17/693

Abstract:
A technique for reducing jitter in an oscillating signal generated by an oscillator circuit includes reducing feedback of gate leakage current while increasing electrostatic discharge protection and reducing regulated power supply requirements of the oscillator circuit, as compared to conventional oscillator circuits. A circuit includes a first integrated circuit terminal and a thick gate native transistor of a first conductivity type having a first gate terminal having a first gate thickness. The first gate terminal is coupled to the first integrated circuit terminal. The thick gate native transistor has a first threshold voltage. The thick gate native transistor is configured as a source follower. The circuit includes a second transistor of the first conductivity type having a second gate terminal with a second gate thickness less than the first gate thickness. The second gate terminal is coupled to a source terminal of the thick gate native transistor.
Public/Granted literature
- US20170317645A1 Leakage Tolerant Oscillator Public/Granted day:2017-11-02
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