Invention Grant
- Patent Title: Portion isolation architecture for chip isolation test
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Application No.: US15188122Application Date: 2016-06-21
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Publication No.: US10067183B2Publication Date: 2018-09-04
- Inventor: Steven M. Douskey , Raghu G. Gaurav , Mary P. Kusko , Hari K. Rajeev
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Steven Meyers
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G01R31/3177

Abstract:
Embodiments include methods, and processing system, and computer program products providing portion isolation design to a chip design to facilitate partial-good portion isolation test of the chip. Aspects include: retrieving a chip design file of a chip, the chip design file having pin related information from a chip design database, generating, via a pin group utility module, a pin group file according to the pin related information retrieved, combining, via a portion wrapper insertion utility module, the pin group file with one or more portion netlists to form one or more localized portion wrapper segments, stitching, via the portion wrapper insertion utility module, the one or more localized portion wrapper segments to form a portion boundary wrapper chain, and inserting, via the portion wrapper insertion utility module, the portion boundary wrapper chain into the chip design file to facilitate partial-good portion isolation test.
Public/Granted literature
- US20170363683A1 PORTION ISOLATION ARCHITECTURE FOR CHIP ISOLATION TEST Public/Granted day:2017-12-21
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