Invention Grant
- Patent Title: Logic analyzer for detecting hangs
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Application No.: US14891337Application Date: 2014-12-13
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Publication No.: US10067871B2Publication Date: 2018-09-04
- Inventor: Rodney E. Hooker , Douglas R. Reed
- Applicant: VIA Alliance Semiconductor Co., Ltd.
- Applicant Address: CN Shanghai
- Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD
- Current Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD
- Current Assignee Address: CN Shanghai
- Agency: McClure, Qualey & Rodack, LLP
- International Application: PCT/IB2014/003174 WO 20141213
- International Announcement: WO2016/092345 WO 20160616
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F9/30 ; G06F9/38 ; G06F9/52 ; G06F12/0855 ; G06F12/0897 ; G06F12/0864

Abstract:
A microprocessor comprises a cache including a tag array; a tagpipe that arbitrates access to the tag array; and a logic analyzer for investigating a starvation, livelock, or deadlock condition. The logic analyzer, which comprises read logic coupled to the tagpipe, is configured to record snapshots of transactions to access the tag array.
Public/Granted literature
- US20160350223A1 LOGIC ANALYZER FOR DETECTING HANGS Public/Granted day:2016-12-01
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