Invention Grant
- Patent Title: Method of bonding supporting substrate with device substrate for fabricating semiconductor device
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Application No.: US15233918Application Date: 2016-08-10
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Publication No.: US10068775B2Publication Date: 2018-09-04
- Inventor: Mika Fujii , Kazuyuki Higashi , Kazumichi Tsumura , Takashi Shirono
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Patterson & Sheridan, LLP
- Priority: JP2015-177931 20150909
- Main IPC: H01L21/304
- IPC: H01L21/304 ; H01L21/265 ; H01L21/683
Abstract:
According to one embodiment, a method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes three steps of a providing step, a bonding step, and a thinning step. In the providing step, a mitigation layer that mitigates warping of the device substrate being thinned by grinding is provided on the supporting substrate. In the bonding step, the device substrate is bonded to the supporting substrate on which the mitigation layer is provided. In the thinning step, the device substrate supported by the supporting substrate is thinned by grinding.
Public/Granted literature
- US20170069503A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Public/Granted day:2017-03-09
Information query
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