Invention Grant
- Patent Title: Self-aligned spacer for cut-last transistor fabrication
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Application No.: US15406114Application Date: 2017-01-13
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Publication No.: US10068805B2Publication Date: 2018-09-04
- Inventor: Ruqiang Bao , Dechao Guo , Zuoguang Liu
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L23/528 ; H01L23/522 ; H01L29/66 ; H01L21/28 ; H01L21/02 ; H01L29/417

Abstract:
Semiconductor devices include one or more semiconductor fins. A gate is formed over the one or more semiconductor fins. A vertical sidewall is formed at a perimeter of the gate, the vertical sidewall having a uniform thickness along its height. A power rail is formed in contact with the vertical sidewall.
Public/Granted literature
- US20180082905A1 SELF-ALIGNED SPACER FOR CUT-LAST TRANSISTOR FABRICATION Public/Granted day:2018-03-22
Information query
IPC分类: