Invention Grant
- Patent Title: Semiconductor device and method of forming cavity in build-up interconnect structure for short signal path between die
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Application No.: US13726467Application Date: 2012-12-24
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Publication No.: US10068843B2Publication Date: 2018-09-04
- Inventor: Reza A. Pagaila
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/56 ; H01L23/31 ; H01L23/498 ; H01L23/538 ; H01L23/552 ; H01L25/065 ; H01L25/00 ; H01L21/768 ; H01L23/34 ; H01L23/00 ; H01L25/10 ; H01L25/16

Abstract:
In a semiconductor device, a first semiconductor die is mounted with its active surface oriented to a temporary carrier. An encapsulant is deposited over the first semiconductor die and temporary carrier. The temporary carrier is removed to expose a first side of the encapsulant and active surface of the first semiconductor die. A masking layer is formed over the active surface of the first semiconductor die. A first interconnect structure is formed over the first side of the encapsulant. The masking layer blocks formation of the first interconnect structure over the active surface of the first semiconductor die. The masking layer is removed to form a cavity over the active surface of the first semiconductor die. A second semiconductor die is mounted in the cavity. The second semiconductor die is electrically connected to the active surface of the first semiconductor die with a short signal path.
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