Invention Grant
- Patent Title: Post-passivation interconnect structure and methods thereof
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Application No.: US15811306Application Date: 2017-11-13
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Publication No.: US10068867B2Publication Date: 2018-09-04
- Inventor: Chien-Chia Chiu , Ming-Yen Chiu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/00 ; H01L23/528 ; H01L23/522 ; H01L23/538

Abstract:
A method includes providing a die including a substrate and a bonding pad over the substrate, forming a connective layer over the die, and forming the landing pad over the connective layer. The forming the connective layer includes depositing a dielectric layer of a dielectric material over the die and patterning the dielectric layer. The patterning the dielectric layer includes forming a supporting pad area and forming a conductive channel area. A portion of the conductive channel area passes at least partially through the supporting pad area. At least one dielectric region interpose the portion of the conductive channel area and the supporting pad area. The forming the connective further includes filling the supporting pad area and the conductive channel area with a conductive material. The supporting pad area of the conductive material forms a supporting pad. The conductive channel area of the conductive material forms a conductive channel.
Public/Granted literature
- US20180068968A1 Post-Passivation Interconnect Structure and Methods Thereof Public/Granted day:2018-03-08
Information query
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