A wiring substrate includes ceramic layers and a conductive member. The ceramic layers have an uppermost ceramic layer and a lowermost ceramic layer. The conductive member includes an upper conductive layer, an internal conductive layer, a lower conductive layer, vias, and a covering layer. The upper conductive layer is disposed on an upper surface of the uppermost ceramic layer. The internal conductive layer is interposed between the ceramic layers. The lower conductive layer is disposed on a lower surface of the lowermost ceramic layer. The vias connect the upper conductive layer, the internal conductive layer, and the lower connective layer. The covering layer covers a portion of the upper conductive layer. The upper conductive layer includes a covered region covered with the covering layer and an element mount region. An upper surface of the element mount region is higher than an upper surface of the covered portion.