The present disclosure is directed to a surge limiting circuit electrically coupleable between a power source and a downstream component. The surge limiting circuit may include a transistor configured to operate in each of a first mode that allows an electric current to flow through the transistor, a second mode that cuts off an electric current from flowing through the transistor, and a third mode that only partially allows an electric current to flow through the transistor while partially cutting off the electric current. The surge limiting circuit may further include a control circuit coupled to the transistor and configured to control operation of the transistor in response to an electrical voltage at the transistor's output. The control circuit may further be configured to repeatedly cycle between controlling operation of the transistor in the first mode and the second mode such that the transistor operates in the third mode.