Methods to minimize the recovered clock jitter
Abstract:
A circuit according to an embodiment includes a first slicer connected to an input port and a threshold circuit connected to a threshold port of the first slicer and configured to generate a first threshold voltage according to at least a first magnitude of a nominal value of a leading bit in a signal received at the input port. The first slicer is configured to slice the signal according to the first threshold voltage. In some embodiments, the threshold circuit calculates the first threshold voltage according to at least the first magnitude of the nominal value of the leading bit in the signal and a second magnitude of an interference voltage caused, in the leading bit, by a preceding bit.
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