Invention Grant
- Patent Title: Methods to minimize the recovered clock jitter
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Application No.: US14936996Application Date: 2015-11-10
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Publication No.: US10069654B2Publication Date: 2018-09-04
- Inventor: Saeid Sadeghi-Emamchaie
- Applicant: Huawei Technologies Co., Ltd.
- Applicant Address: CN Shenzhen
- Assignee: Huawei Technologies Co., Ltd.
- Current Assignee: Huawei Technologies Co., Ltd.
- Current Assignee Address: CN Shenzhen
- Agency: Slater Matsil, LLP
- Main IPC: H03D3/24
- IPC: H03D3/24 ; H04L7/00 ; H04L25/03 ; H04L27/26

Abstract:
A circuit according to an embodiment includes a first slicer connected to an input port and a threshold circuit connected to a threshold port of the first slicer and configured to generate a first threshold voltage according to at least a first magnitude of a nominal value of a leading bit in a signal received at the input port. The first slicer is configured to slice the signal according to the first threshold voltage. In some embodiments, the threshold circuit calculates the first threshold voltage according to at least the first magnitude of the nominal value of the leading bit in the signal and a second magnitude of an interference voltage caused, in the leading bit, by a preceding bit.
Public/Granted literature
- US20170134189A1 Methods to Minimize the Recovered Clock Jitter Public/Granted day:2017-05-11
Information query
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