Memory system with power-off detection and recovery mechanism
Abstract:
A memory system may include: a memory device including a plurality of memory blocks each memory block having a plurality of pages; and a controller suitable for performing a plurality of operations to first memory blocks among the memory blocks at a first time, recording a checkpoint information for the operations in the memory blocks, selecting second memory blocks among the first memory blocks through the checkpoint information at a second time after a power-off in the memory system while performing the operations, and performing a dummy write operation to the second memory blocks.
Public/Granted literature
Information query
Patent Agency Ranking
0/0