Invention Grant
- Patent Title: Method for manufacturing multilayer wiring substrate
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Application No.: US15027756Application Date: 2014-09-24
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Publication No.: US10076044B2Publication Date: 2018-09-11
- Inventor: Nobuyuki Yoshida
- Applicant: HITACHI CHEMICAL COMPANY, LTD.
- Applicant Address: JP Tokyo
- Assignee: HITACHI CHEMICAL COMPANY, LTD.
- Current Assignee: HITACHI CHEMICAL COMPANY, LTD.
- Current Assignee Address: JP Tokyo
- Agency: Fitch Even Tabin & Flannery, LLP
- Priority: JP2013-211871 20131009; JP2014-147757 20140718
- International Application: PCT/JP2014/075257 WO 20140924
- International Announcement: WO2015/053084 WO 20150416
- Main IPC: H05K3/42
- IPC: H05K3/42 ; H05K3/00 ; H05K3/46

Abstract:
The present invention is a method for manufacturing a multilayer wiring board having (1) a step of providing with a hole for a via hole from a metal foil for an upper layer wiring pattern to an inner layer wiring pattern by using a conformal method or a direct laser method, and (2) a step of forming a via hole by forming electrolytic filling plating layers in the hole for a via hole, wherein the formation of the electrolytic filling plating layers in the step (2) is carried out by repeating change in electric current density of temporarily decreasing the electric current density of electrolytic filling plating in the middle of the electrolytic filling plating and then increasing it again, two or more times before the electrolytic filling plating layers block an opening of the hole for a via hole.
Public/Granted literature
- US20160242299A1 METHOD FOR MANUFACTURING MULTILAYER WIRING SUBSTRATE Public/Granted day:2016-08-18
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