A signal transfer device includes an interface and a read and write circuit. The interface has a posted write data protocol and transfers data to a memory control device that controls access to a shared memory. If a write request for writing data to the shared memory via the interface is issued, the read and write circuit acquires a write address from the write request, and puts a read request for reading data from the write address on standby until a transfer amount of write data exceeds a total size of buffers on a signal transfer path to the shared memory.