A method of implementing fault tolerance in computer memory includes translating a logical address to a first physical address for a first memory location in the computer memory. The computer memory includes redundant memory locations. A second memory location selected from the redundant memory locations is used instead of the first memory location in response to information characterizing the first memory location as faulty. Also, error correction coding (ECC) is performed at least two times on data written to the computer memory and read from the computer memory; the ECC is performed in the computer memory and outside the computer memory. Furthermore, in response to identifying a defective first pin on a memory module, an input from the defective pin is routed to a redundant second pin on the module, and an output from the second pin is routed to a destination on the memory module.