Invention Grant
- Patent Title: Method of forming interconnects for semiconductor devices
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Application No.: US15082588Application Date: 2016-03-28
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Publication No.: US10079147B2Publication Date: 2018-09-18
- Inventor: Yong Kong Siew , Sung Yup Jung
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Law, PLLC
- Priority: KR10-2015-0108958 20150731
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/033 ; H01L21/324 ; H01L21/768

Abstract:
A method of forming interconnects for semiconductor devices includes forming a lower insulating layer and a lower interconnect on a semiconductor substrate, forming an insulating pattern layer on the lower interconnect through self-assembly, forming an interlayer insulating layer and a trench mask on the insulating pattern layer, forming a preparatory via hole allowing the insulating pattern layer to be exposed by removing a portion of the interlayer insulating layer, forming a trench by etching the interlayer insulating layer using the trench mask, forming a via hole allowing the lower interconnect to be exposed by selectively etching the insulating pattern layer within the preparatory via hole, and filling the trench and the via hole with an conductive material.
Public/Granted literature
- US20170033006A1 METHOD OF FORMING INTERCONNECTS FOR SEMICONDUCTOR DEVICES Public/Granted day:2017-02-02
Information query
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