Invention Grant
- Patent Title: Formation method of semiconductor device structure using multilayer resist layer
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Application No.: US15461846Application Date: 2017-03-17
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Publication No.: US10079178B1Publication Date: 2018-09-18
- Inventor: Po-Ju Chen , Yi-Wei Chiu , Fang-Yi Wu , Chih-Hao Chen , Wen-Yen Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/033 ; H01L21/311 ; H01L21/027

Abstract:
Formation methods of a semiconductor device structure are provided. The method includes forming a bottom layer, a middle layer and an upper layer over a substrate, developing the upper layer to form an upper pattern with a first opening exposing the middle layer and a sidewall of the upper pattern. The upper pattern has a top surface. The method further includes conformally forming a protective layer over the upper pattern and the exposed middle layer, anisotropically etching the protective layer to leave a portion of the protective layer over the sidewall of the upper pattern and expose the middle layer, etching the middle layer not covered by the upper pattern and the portion of the protective layer to form a middle pattern with a second opening exposing the bottom layer, and etching the bottom layer though the second opening of the middle pattern.
Public/Granted literature
- US20180269102A1 FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE USING MULTILAYER RESIST LAYER Public/Granted day:2018-09-20
Information query
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