Invention Grant
- Patent Title: Package substrate having a plurality of chips electrically connected by conductive vias and wiring bonding
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Application No.: US15798698Application Date: 2017-10-31
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Publication No.: US10079220B2Publication Date: 2018-09-18
- Inventor: Chu-Chin Hu , Shih-Ping Hsu
- Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.
- Applicant Address: KY Grand Cayman
- Assignee: PHOENIX & CORPORATION
- Current Assignee: PHOENIX & CORPORATION
- Current Assignee Address: KY Grand Cayman
- Agency: WPAT, PC
- Priority: TW105136014A 20161104
- Main IPC: H01L23/34
- IPC: H01L23/34 ; H01L21/4763 ; H01L25/065 ; H01L21/768 ; H01L23/48 ; H01L23/31 ; H01L23/522 ; H01L23/528 ; H01L23/00

Abstract:
This disclosure provides a package substrate and its fabrication method. The package substrate includes: a dielectric body; a first circuit device disposed in the dielectric body, the first circuit device comprising a first terminal and a second terminal at a top of the first circuit device; a second circuit device disposed in the dielectric body, the second circuit device comprising a third terminal at a top of the second circuit device; a first conductive pillar formed in the dielectric body and connected to the first terminal; a first bonding wire connecting the second terminal and the third terminal; and a redistribution layer comprising a first conductive wire formed on the dielectric body, the conductive wire connected to the first conductive pillar.
Public/Granted literature
- US20180130771A1 PACKAGE SUBSTRATE AND ITS FABRICATION METHOD Public/Granted day:2018-05-10
Information query
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