Invention Grant
- Patent Title: Interconnect structures for assembly of semiconductor structures including at least one integrated circuit structure
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Application No.: US15327249Application Date: 2015-08-11
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Publication No.: US10079224B2Publication Date: 2018-09-18
- Inventor: Rabindra N. Das , Donna-Ruth W. Yost , Chenson Chen , Keith Warner , Steven A. Vitale , Mark A. Gouker , Craig L. Keast
- Applicant: Massachusetts Institute of Technology
- Applicant Address: US MA Cambridge
- Assignee: Massachusetts Institute of Technology
- Current Assignee: Massachusetts Institute of Technology
- Current Assignee Address: US MA Cambridge
- Agency: Daly, Crowly, Mofford & Durkee, LLP
- International Application: PCT/US2015/044651 WO 20150811
- International Announcement: WO2016/025478 WO 20160218
- Main IPC: H01L25/10
- IPC: H01L25/10 ; H01L23/00 ; H01L23/498 ; H01L25/00

Abstract:
A semiconductor structure includes at least two substrate layers, each of the at least two substrate layers having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes a substrate joining layer disposed between and coupled to the second surface of a first one of the at least two substrate layers and the first surface of a second one of the at least two substrate layers. The substrate joining layer includes at least one integrated circuit (IC) structure disposed between the first and second surfaces of said substrate joining layer. A corresponding method for fabricating a semiconductor structure is also provided.
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