Invention Grant
- Patent Title: Chip scale package and related methods
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Application No.: US15674738Application Date: 2017-08-11
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Publication No.: US10079254B2Publication Date: 2018-09-18
- Inventor: Bingzhi Su , Derek Gochnour , Larry Kinsman
- Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Agency: IPTechLaw
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L27/146 ; H01L21/48 ; H01L21/56 ; H01L23/08 ; H01L23/10 ; H01L23/31 ; H01L23/00

Abstract:
Implementations of semiconductor packages may include: a die coupled to a glass lid; one or more inner walls having a first material coupled to the die; an outer wall having a second material coupled to the die; and a glass lid coupled to the die at the one or more inner walls and at the outer wall; wherein the outer wall may be located at the edge of the die and the glass lid and the one or more inner walls may be located within the perimeter of the outer wall at a predetermined distance from the perimeter of the outer wall; and wherein a modulus of the first material may be lower than a modulus of the second material.
Public/Granted literature
- US20180019275A1 CHIP SCALE PACKAGE AND RELATED METHODS Public/Granted day:2018-01-18
Information query
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