Invention Grant
- Patent Title: Method to form strained nFET and strained pFET nanowires on a same substrate
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Application No.: US15450756Application Date: 2017-03-06
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Publication No.: US10079303B2Publication Date: 2018-09-18
- Inventor: Kangguo Cheng , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Daniel P. Morris, Esq.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L27/12 ; H01L21/84 ; H01L29/06 ; H01L21/02 ; H01L21/3065
Abstract:
A semiconductor is provided that includes an nFET gate structure straddling over a first nanowire stack and a portion of a first SiGe layer having a first Ge content. The first nanowire stack comprises alternating layers of a tensily strained silicon layer, and a second SiGe layer having a second Ge content that is greater than the first Ge content and being compressively strained. Portions of the tensily strained silicon layers extend beyond sidewalls surfaces of the nFET gate structure and are suspended. The structure further includes a pFET gate structure straddling over a second nanowire stack and another portion of the first SiGe layer. The second nanowire stack comprises alternating layers of the tensily strained silicon layer, and the second SiGe layer. Portions of the second SiGe layers extend beyond sidewalls surfaces of the pFET gate structure and are suspended.
Public/Granted literature
- US20170179289A1 METHOD TO FORM STRAINED nFET AND STRAINED pFET NANOWIRES ON A SAME SUBSTRATE Public/Granted day:2017-06-22
Information query
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