Invention Grant
- Patent Title: Vertical transistor structure with looped channel
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Application No.: US15682631Application Date: 2017-08-22
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Publication No.: US10079308B1Publication Date: 2018-09-18
- Inventor: Shesh Mani Pandey , Hui Zang , Josef S. Watts
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Hoffman Warnick LLC
- Agent Yuanmin Cai
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L29/786 ; H01L21/768 ; H01L29/66 ; H01L21/8234

Abstract:
The disclosure provides a vertical FinFET structure, including: a substrate including a first source/drain region; a looped channel region positioned on the first source/drain region of the substrate, the looped channel region having an inner perimeter which surrounds a hollow interior of the looped channel region; a first gate positioned within the hollow interior of the looped channel region, wherein the first gate is formed onto the looped channel region along the inner perimeter of the looped channel region; and a second source/drain region positioned on and overlying an upper surface of the looped channel region.
Information query
IPC分类: