Staggered switching in a load driver
Abstract:
An apparatus comprises multiple impedances and multiple pairs of transistors. Each pair connects to an impedance. Each pair includes high and low side transistors. The high side transistors and the low side transistors are connected each other and to a first terminal of the corresponding impedance, wherein second terminals of the impedances are connected to each other. The apparatus also comprises a staggered signal transistor driver to assert separate delayed high side signals to control inputs of the high side transistors. The delayed high side signals are time delayed with respect to each other. The driver asserts separate delayed low side signals to control inputs of the low side transistors.
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