A high density, high speed ROIC uses in-pixel integration capacitors and comparators to convert each pixel charge to a train of pulse spikes which increment a capacitor to successive, discrete charge values that represent a digital, non-binary count value of an in-pixel multi-value digital counter (MVDC). The MVDC can include a plurality of stages whereby comparators limit the maximum count of each stage and increment subsequent stages. The maximum count can be a power of two for subsequent direct ADC conversion to binary. The count values and the residual integration capacitor charge can be read out by ramping the comparator reference inputs and measuring the comparator output timings, effectively forming partially in-pixel single-slope ADC's. The comparators can include temporary internal positive feedback to maintain consistency of the spike pulses to better than 10%.