Embodiments include methods, design layout optimization systems, and computer program products for optimizing design layout of integrated circuits. Aspects include receiving a design layout of an integrated circuit from a design layout tool module, identifying a critical pitch in the design layout received, searching design rules forming design arc limited by identified critical pitch from a set of design rules associated with the received design layout, extracting a process variation and one or more failure mechanisms of design layout based on critical pitch and rules forming design arc identified, performing layout based ground rule calculation based on the process variation and the one or more failure mechanisms extracted, determining whether wafer risks exist in the design layout, responsive to determining the wafer risks exist in the design layout, revising the design layout and performing additional layout based ground rule calculation after the revision, and otherwise, outputting an optimized design layout.